Modern electronic circuits and devices are integrated on a smaller surface and run at a frequency often exceeding 1 GHz to speed up logic transitions and data transfer. In order to detect manufacturing defects or flaws that occur at an operating frequency of the electronic circuits, these circuits and devices are tested at or near their operating frequencies, using so called at-speed clocks. It is exceedingly difficult and expensive to test electronic chips, integrated circuits, devices, and/or printed circuit boards using automated test equipment (ATE) that provide such high frequency clocks. Instead, high frequency clocks are often derived on-chip from a lower clock frequency by running one or more Phase-Locked Loop (PLL) circuits. For example, a relatively slow 100 MHz input clock from an oscillator supplied by an ATE or a test board is multiplied in frequency using a PLL to produce a 2 GHz output clock. The faster output clock is used to run state machines for testing logic circuits operating at different clock frequencies in a device under test (DUT) or logic under test (LUT).
To avoid hefty expenses and potential technical troubles for providing high-speed clocks in an ATE, a technique called on-product clock generation (OPCG) is utilized. OPCG domain logic passes through the functional clock as unmodified during normal operation, and provides test clock sequences during test operations. The OPCG domain logic multiplies input clock frequencies using one or more PLLs to generate high frequency clocks and divides the PLL output clock using clock dividers to generate a lower frequency clock to run other domains that do not run at the higher frequency of the direct PLL output. These clock signals generated from the PLL and/or the clock dividers are used to run state machines for each of the internal clock domains for the device being tested.
State machines for chip testing in a test application are programmable and run from an at-speed clock generated from OPCG domain logic (PLLs and optionally with clock dividers). Programming of these state machines is typically accomplished by including programming bits within test scan chains of the DUT. As each test's stimuli are loaded via test scan chains, the OPCG domain logic is loaded according to the programming bits via the test scan chains. However, typical state machines do not provide sufficient flexibility as to how the pulses are generated for each clock domain.
Programming a state machine that uses OPCG domain logic poses several problems. First, if a decompression logic circuit is used to load scan chains, the OPCG programming bits must be resolved from the test data that is pushed through the decompression logic. Decompression of the test data to resolve the OPCG programming bits consumes valuable bandwidth and requires additional ‘care’ bits that compete with the ATPG ‘care’ bits that are necessary when mapping automatic test pattern generation (ATPG) tests through the decompression logic. The OPCG programming bits may be forced into dedicated scan chains that are fed directly via separate scan-in pins to avoid competition for scan-in data bandwidth with ATPG care bits and/or other OPCG programming bits in other scan chains. This approach, however, requires additional scan-in pins and/or removes the bandwidth of the scan-in pins feeding just the OPCG programming scan chains from being used to load care bits for normal scan chains, which will have a direct impact on the overall compression efficiency by either making normal scan chains longer or by forcing more test patterns to be generated.
Secondly, when there are many internal clock domains that communicate with each other in some fashion, the uncertain and effectively asynchronous timing of the OPCG-generated clocks to different clock domains makes it very difficult, if not impossible, to deal with race conditions that occur when the clock domains that communicate with each other are clocked at the same time. To resolve these issues with race conditions, only one clock domain is typically pulsed at a time in any one test. Pulsing several clock domains in the same test may be allowed if those clock domains do not communicate with each other. Testing is more efficient when multiple communicating domains can be pulsed in a single test.
Many of today's sophisticated chip designs include multiple internal cores (e.g., processor, memory, I/Os) that run on different clock domains and frequencies. It is common to see chips with hundreds of internal clock domains. If a small number of clock domains are pulsed in each test, the number of tests needed to test the whole chip goes up exponentially, increasing the total cost for testing. Only a few clocks in each test may be pulsed to reduce the chance for delta-I noise caused by excessive switching, often called “simultaneous switching noise” on the power rails. The more domains pulsed simultaneously or nearly simultaneously, the more switching activity occurs, thus the higher is the chance for having switching noise in the power rails.
The various embodiments described herein propose new approaches for programming state machines that generate clock pulses for each internal clock domain.